Embodiments relate to a semiconductor device and a method of fabricating the semiconductor device. Relatively high voltage devices may be used as core parts in semiconductor devices for vehicles, networks, and display driving technologies. For example, a 15V-grade bidirectional relatively high voltage device may be integrated with a relatively low voltage device in the same chip. The 15V-grade bidirectional relatively high voltage device may be used in an output end of a data driver integrated circuit (IC) device of a liquid crystal display (LCD) or organic light emitting diode (OLED) display.
For example, if a driver IC device for a display has 240 to 640 terminals in a single output end, uniformity of the terminals may directly effect image uniformity of the display. In some applications, it may be important that an output end of a driver IC device has substantially uniform electrical characteristics.
Some high voltage devices may be n type metal oxide semiconductor (NMOS) transistors. Such design of NMOS transistor may include a source and a drain disposed in an n type drift region within a p type well on a substrate, and a gate may be disposed on a gate dielectric layer. Spacers may be disposed on at least one of the side walls of the gate. An NMOS transistor may be electrically connected to an external device through a source electrode, a gate electrode, and a drain electrode, which may be insulated by an interlayer dielectric layer.
A process of fabricating a relatively high voltage NMOS device may include at least one of: (1) A wafer as a substrate may be prepared. (2) A mask pattern for forming a high voltage (HV) well may be formed over the substrate. (3) P type impurity ions may be implanted into the substrate. (4) A relatively high voltage p type well may be formed through a drive-in process at relatively high temperature (e.g., 1200° C.) in order to diffuse the implanted impurity ions and to fabricate a semiconductor device having a relatively high breakdown voltage. (5) Another mask pattern for forming a drift region may be formed. N type impurity ions may be implanted into the substrate through the mask pattern. (6) N type drift region may be formed within the relatively high voltage p type well through a relatively high temperature drive-in process for maximizing a breakdown voltage.
In some designs, a well region and a drift region may be formed for a relatively high voltage NMOS device. A process of fabricating a relatively low voltage device on the same wafer may be also performed. For example, a device isolation oxide layer may be formed on a substrate (e.g. through a local oxidation of silicon (LOCOS) process) and a relatively low voltage (LV) well pattern may be formed. Then, ions may be implanted into the substrate through the low voltage (LV) well pattern to form a low voltage well.
Relatively high voltage devices are required to have relatively a minimum channel resistance and resist some breakdown voltage. Referring to FIGS. 9 and 10, in some designs, a field-plate-on-oxide structure may be used to maximize breakdown voltage. Referring to FIG. 9, a shallow trench isolation (STI) structure may be used to form a field-plate-on-oxide structure. In some designs, a current path may be maximized by the depth of the STI structure, so as to maximize on-resistance (Ron). Referring to FIG. 10, a dielectric layer that is relatively thin (compared to an STI structure) may be used to form a field-plate-on-oxide structure. In some designs, additional processes may be required.